منابع مشابه
Reduced Hardware NOREC
The most promising Hybrid TM algorithms to date have been those designed around the NORec STM, because they allow to limit the overall need to instrument instructions in the algorithms all hardware fast-path. However, in order to provide opacity in the hardware transactions, the shared “clock” of the NORec STM must be read at the start of the hardware transaction, which adds it to the track set...
متن کاملReduced Hardware NOREC: An Opaque Obstruction-Free and Privatizing HyTM
This paper presents a reduced-hardware (RH) version of the promising NORec Hybrid TM algorithm. Instead of an all-software slow path, in RH transactions, part of the slow-path is executed using a short hardware transaction. The purpose of this hardware component is not to speed up the slow-path (though this is a side effect). Rather, using it we are able to eliminate virtually all of the instru...
متن کاملReduced Hardware Lock Elision
Hardware lock elision (HLE) concurrently executes lock critical sections as hardware transactions, but fallbacks to the original sequential lock fallback path when some hardware transaction fails. Recent software-assisted lock-removal based schemes provide a better concurrency by sacrificing safety (opacity). Hardware transactions can execute at the same time with the lock fallback path as long...
متن کاملNoReC: The Norwegian Review Corpus
This paper presents the Norwegian Review Corpus (NoReC), created for training and evaluating models for document-level sentiment analysis. The full-text reviews have been collected from major Norwegian news sources and cover a range of different domains, including literature, movies, video games, restaurants, music and theater, in addition to product reviews across a range of categories. Each r...
متن کاملHybrid TM Using NOrec STM
Transactional memory (TM) aims to simplify parallel programming by providing serializable memory transactions as an extension to the system’s memory model. In the context of increasing numbers of on-chip processor cores, Sun’s Rock processor [3] and AMD’s proposed Advanced Synchronization Facility (ASF) [1] suggest that commercial support for best-effort hardware TM (HTM) may finally be forthco...
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ژورنال
عنوان ژورنال: ACM SIGPLAN Notices
سال: 2015
ISSN: 0362-1340,1558-1160
DOI: 10.1145/2775054.2694393